p51 Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels

Abstract—This paper presents a low-power LDPC decoder
design for additive white Gaussian noise (AWGN) channels

p45 Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

I. INTRODUCTION
II. THE PROCESSING ELEMENT
III. PE IMPLEMENTATION STRATEGIES
A. Static CMOS implementation
B. Dynamic Domino implementation
Dynamic Domino circuits have traditionally been known
to provide high operating speeds [4].

In the domino-based implementation of the PE, all the
critical arithmetic circuits have been implemented using
dynamic domino logic style

(page 4)
It is worth noting that even though the data path is dynamic,
the remainder of the circuitry in the RC is static

The input registers, used in our dynamic implementation, are
based on a special static-dynamic interface latches called
Entry Latches (ELATs) [7] used in the Itanium processor

At the output stage, another type of register called pulseto-
level converter was used [8].

C. Data Driven Dynamic Logic Implementation

(page 5)

IV. RESULTS
After preliminary evaluations using pre-layout simulations,
custom layouts were designed.

Extensive post layout simulations using the TT 25°C
process corner were performed on the data paths to evaluate
their performance in terms of speed and power consumption

(page 5 col 2)
The domino design, exhibits an operating frequency over
1GHZ with 8% and 18% more silicon density compared to the
D3L and static counterparts, respectively.

The D3L data path appears ideal for GHz range
operations with 10% speed and 15 % energy consumption
advantages over the corresponding domino circuit.
(D3L is considered at low cost solution that can achieve
most benefits of domino)